Huawei Technologies claims it has developed an alternative path to advanced chip production without access to EUV lithography, outlining plans to achieve transistor densities on par with a 1.4nm-class process by 2031.
Unable to buy ASML’s most advanced equipment because of US export restrictions, the Chinese tech giant is pursuing a different strategy that focuses on rethinking chip design and manufacturing rather than matching traditional lithography methods. Speaking at an event in Shanghai on Monday, chip division president He Tingbo described the approach as “feasible and affordable.”
Huawei’s approach focuses on stacking several layers of circuitry within a single chip and improving the connections that move data between them. Instead of relying on ever-smaller components, the company aims to improve performance through efficiency, reflecting a wider industry move toward 3D chip designs and advanced packaging as transistor scaling nears its limits.
Part of the effort operates under the name “LogicFolding,” a design framework Huawei says will be included in next-generation Kirin smartphone chips expected later this year. The architecture is intended to reorganize processing units and their communication pathways, with similar techniques also being adapted for AI chips, where data movement plays a key role alongside computing power.
Huawei has spent six years developing its semiconductor capabilities under growing restrictions. The company was placed on a US trade blacklist in 2019 and has faced stricter controls on advanced chip technology since 2022. According to Huawei, 381 chip models have already entered mass production using related techniques, although independent performance comparisons with competing products from established manufacturers have not been published.
Analysts describe Huawei’s progress as significant, though questions remain about whether it can scale effectively. Lian Jye Su, a Singapore-based analyst at Omdia, told the Wall Street Journal that while it is unclear whether Huawei will gain a clear advantage, the effort represents an alternative route and a breakthrough achieved despite supply chain pressures.
Stacking circuits creates significant engineering challenges. Densely layered components can lead to heat buildup and reliability concerns, while coordinating processes across several logic layers requires more sophisticated design software. People familiar with Huawei’s development efforts said the company only achieved more stable results within the past year. Demonstrating reliable performance at scale, particularly in data center environments, will likely require further testing and deeper collaboration with hardware and infrastructure partners.
If Huawei achieves its 2031 target, the effects could be significant. A viable alternative to traditional manufacturing methods could lower production costs and reduce the industry’s reliance on a small number of equipment suppliers. In the shorter term, the effort reflects how geopolitical pressure is driving experimentation in chip design and may influence the direction of next-generation semiconductor development.
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